The present invention relates generally to integrated circuits including internal memory and, more particularly, to methods and apparatus for testing memory in a low power state.
In order to test an operation of a memory device, such as an SRAM, it is known to perform a retention test in which data is written to the memory device and, after a period of waiting, is read back from the memory and verified as being consistent with that initially written to the memory device.
Integrated circuits may be operated in a low leakage mode, such as a low leakage stop (LLS) mode in which a clock for at least a part of the circuit is stopped. The supply of power to parts of the circuit may also be reduced.
A retention test may be performed on the memory device in the stop mode. However such testing may not be indicative of actual operating conditions in the stop mode since at least some inputs to the memory device may still be powered during the testing, which is not indicative of conditions during the actual stop mode. Accordingly, it would be advantageous to be able to test memory retention under actual conditions for various modes of operation.